Memory device, programmable resistance memory cell and memory array

ABSTRACT

A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices. In one implementation, a non-volatile resistance variable device in a highest resistance state for a given ambient temperature and pressure includes a resistance variable chalcogenide material having metal ions diffused therein. Opposing first and second electrodes are received operatively proximate the resistance variable chalcogenide material. At least one of the electrodes has a conductive projection extending into the resistance variable chalcogenide material.

TECHNICAL FIELD

This invention relates to non-volatile resistance variable devices and methods of forming the same.

BACKGROUND OF THE INVENTION

Semiconductor fabrication continues to strive to make individual electronic components smaller and smaller, resulting in ever denser integrated circuitry. One type of integrated circuitry comprises memory circuitry where information is stored in the form of binary data. The circuitry can be fabricated such that the data is volatile or non-volatile. Volatile storing memory devices result in loss of data when power is interrupted. Non-volatile memory circuitry retains the stored data even when power is interrupted.

This invention was principally motivated in making improvements to the design and operation of memory circuitry disclosed in the Kozicki et al. U.S. Pat. Nos. 5,761,115; 5,896,312; 5,914,893; and 6,084,796, which ultimately resulted from U.S. patent application Ser. No. 08/652,706, filed on May 30, 1996, disclosing what is referred to as a programmable metalization cell. Such a cell includes opposing electrodes having an insulating dielectric material received therebetween. Received within the dielectric material is a fast ion conductor material. The resistance of such material can be changed between highly insulative and highly conductive states. In its normal high resistive state, to perform a write operation, a voltage potential is applied to a certain one of the electrodes, with the other of the electrode being held at zero voltage or ground. The electrode having the voltage applied thereto functions as an anode, while the electrode held at zero or ground functions as a cathode. The nature of the fast ion conductor material is such that it undergoes a chemical and structural change at a certain applied voltage. Specifically, at some suitable threshold voltage, plating of metal from metal ions within the material begins to occur on the cathode and grows or to progresses through the fast ion conductor toward the other anode electrode. With such voltage continued to be applied, the process continues until a single conductive dendrite or filament extends between the electrodes, effectively interconnecting the top and bottom electrodes to electrically short them together.

Once this occurs, dendrite growth stops, and is retained when the voltage potentials are removed. Such can effectively result in the resistance of the mass of fast ion conductor material between electrodes dropping by a factor of 1,000. Such material can be returned to its highly resistive state by reversing the voltage potential between the anode and cathode, whereby the filament disappears. Again, the highly resistive state is maintained once the reverse voltage potentials are removed. Accordingly, such a device can, for example, function as a programmable memory cell of memory circuitry.

The preferred resistance variable material received between the electrodes typically and preferably comprises a chalcogenide material having metal ions diffused therein. A specific example is germanium selenide with silver ions. The present method of providing the silver ions within the germanium selenide material is to initially deposit the germanium selenide glass without any silver being received therein. A thin layer of silver is thereafter deposited upon the glass, for example by physical vapor deposition or other technique. An exemplary thickness is 200 Angstroms or less. The layer of silver is irradiated, preferably with electromagnetic energy at a wavelength less than 500 nanometers. The thin nature of the deposited silver enables such energy to pass through the silver to the silver/glass interface effective to break a chalcogenide bond of the chalcogenide material, thereby effecting dissolution of silver into the germanium selenide glass. The applied energy and overlying silver result in the silver migrating into the glass layer such that a homogenous distribution of silver throughout the layer is ultimately achieved.

It can be challenging to etch and to chemical-mechanical polish metal ion containing chalcogenide materials. Accordingly it would be desirable to develop memory cell fabrication methods which avoid one or both of etching or polishing such materials. It would also be desirable to develop alternate methods from that just described which incorporate the metal ions into chalcogenide materials. While the invention was principally motivated in achieving objectives such as these, the invention is in no way so limited. The artisan will appreciate applicability of the invention in other aspects of processing involving chalcogenide materials, with the invention only being limited by the accompanying claims as literally worded and as appropriately interpreted in accordance with the doctrine of equivalents.

SUMMARY

The invention includes non-volatile resistance variable devices and methods of forming the same. In one implementation, a method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. In one implementation, a method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices.

In one implementation, a non-volatile resistance variable device in a highest resistance state for a given ambient temperature and pressure includes a resistance variable chalcogenide material having metal ions diffused therein. Opposing first and second electrodes are received operatively proximate the resistance variable chalcogenide material. At least one of the electrodes has a conductive projection extending into the resistance variable chalcogenide material.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment in process in accordance with an aspect of the invention.

FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.

FIG. 3 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 2.

FIG. 4 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 3.

FIG. 5 is a view of the FIG. 1 wafer fragment at an alternate processing step subsequent to that shown by FIG. 3.

FIG. 6 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 4.

FIG. 7 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 6.

FIG. 8 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

Referring to FIG. 1, a semiconductor wafer fragment 10 is shown in but one preferred embodiment of a method of forming a non-volatile resistance variable device. By way of example only, example such devices include programmable metalization cells and programmable optical elements of the patents referred to above, further by way of example only, including programmable capacitance elements, programmable resistance elements, programmable antifuses of integrated circuitry and programmable memory cells of memory circuitry. The above patents are herein incorporated by reference. The invention contemplates the fabrication techniques and structure of any existing non-volatile resistance variable device, as well as yet-to-be developed such devices. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated. Further, it will be appreciated by the artisan that “resistance setable semiconductive material” and “resistance variable device” includes materials and devices wherein a property or properties in addition to resistance is/are also varied. For example, and by way of example only, the material's capacitance and/or inductance might also be changed in addition to resistance.

Semiconductor wafer fragment 10 comprises a bulk monocrystalline semiconductive material 12, for example silicon, having an insulative dielectric layer 14, for example silicon dioxide, formed thereover. A conductive electrode material 16, also termed a first metal layer, is formed over and on dielectric layer 14. By way of example only, preferred materials include any of those described in the incorporated Kozicki et al. patents referred to above in conjunction with the preferred type of device being fabricated. Layer 16 might constitute a patterned electrode for the preferred non-volatile resistance variable device being fabricated. Alternately by way of example only, layer 16 might constitute a patterned line or extension of a field effect transistor gate, with a subsequently deposited layer principally serving essentially as the electrode. An example preferred material for layer 16 is elemental tungsten deposited to an exemplary thickness of from about 100 Angstroms to about 1000 Angstroms. In the illustrated example, layer 16 has been patterned, and another dielectric layer 17 has been deposited and planarized as shown.

A second metal layer 18 is formed (preferably by a blanket deposition) on first metal layer 16. An exemplary preferred material in conjunction with the non-volatile resistance variable device being fabricated is elemental silver. A preferred thickness for layer 18 is from about 175 Angstroms to about 300 Angstroms.

Referring to FIG. 2, second metal layer 18 is formed into a structure 20, and first metal layer 16 is outwardly exposed. Such is preferably conducted by subtractive patterning of metal layer 18, for example by photolithographic patterning and etch. In one implementation, structure 20 can be considered as comprising a metal mass projecting from underlying substrate material and having outer surfaces comprised of a top surface 22 and opposing side surfaces 24 which join with top surface 22 at respective angles. The preferred angles are preferably within about 15° of normal, with normal angles being shown in the figures.

Referring to FIG. 3, a chalcogenide material 26 is formed over the substrate on second metal structure 20 outer surfaces 22 and 24, and on exposed first metal layer 16. Such is preferably formed by blanket physical vapor deposition. A preferred deposition thickness for layer 26 is preferably less than three times the thickness of deposited layer 18, with an example being from about 525 Angstroms to about 900 Angstroms. More preferred is a thickness to provide layer 18 at 20% to 50% of layer 26 thickness. Exemplary preferred chalcogenide materials include those disclosed in the Kozicki et al. patents referred to above. Specific preferred examples include a chalcogenide material having metal ions diffused therein represented by the formula Ge_(x)A_(y), where “A” is selected from the group consisting of Se, Te and S and mixtures thereof. The illustrated example provides but one possible example of surrounding the exposed outer surfaces of a projecting metal mass with chalcogenide material in accordance with but one aspect of the invention.

Referring to FIG. 4, irradiating is conducted through chalcogenide material 26 to patterned second metal 18 effective to break a chalcogenide bond of the chalcogenide material at an interface with the patterned second metal outer surfaces and the chalcogenide material, and to diffuse at least some of second metal 18 outwardly into the chalcogenide material. Metal doped material 27 is formed thereby. Therefore as shown in the preferred embodiment, only a portion of blanket deposited chalcogenide material layer 26 is doped with second metal 18. A preferred irradiating includes exposure to actinic radiation having a wavelength below 500 nanometers, with radiation exposure at between 404-408 nanometers being a more specific example. A specific example in a suitable UV radiation flood exposure tool is 4.5 mW/cm², 15 minutes, 405 nm wavelength, at room ambient temperature and pressure.

In the depicted and preferred embodiment, the irradiating diffuses only some of the metal from layer 18 outwardly into chalcogenide material, leaving a remnant structure 20 a. Accordingly, the projecting metal mass 20 a has a shape after the irradiating which is maintained in comparison to original shape 20, but at a reduced size. FIG. 5 illustrates a lesser preferred alternate embodiment 10 a whereby the irradiating and/or layer dimensions might be modified such that the irradiating diffuses all of projecting metal mass 20 outwardly into the chalcogenide material.

The preferred exemplary tungsten material of layer 16 does not appreciably diffuse into layer 26. Referring to FIG. 6 and regardless, chalcogenide material 26 not doped with metal 18 is substantially selectively etched from metal doped portion 27 of the chalcogenide material. In the context of this document, “substantially selective” means a relative etch ratio of layer 26 relative to layer 27 or at least 3:1. In the illustrated and preferred embodiment, such etching is preferably conducted to remove all of chalcogenide material 26 which has not been doped with metal 18. The preferred etching comprises dry anisotropic etching, preferably dry plasma anisotropic etching. A principle preferred component of such etching gas comprises CF₄. Additional preferred gases in the chemistry include C₂F₆ and C₄F₈. Top power is preferably maintained at 500 watts, with the lower wafer susceptor being allowed to float. Susceptor temperature is preferably maintained at about 25° C., and an exemplary reactor pressure is 50 mTorr. By way of example only, a specific example in a reactive ion etcher is CF₄ at 50 sccm, Ar at 25 sccm, susceptor temperature at 25° C., pressure of 50 mTorr and top power at 500 Watts.

Referring to FIG. 7, an insulating layer 30 has been deposited and metal doped chalcogenide material 27 has been exposed. An example and preferred material for layer 30 is silicon nitride.

Referring to FIG. 8, an outer conductive electrode layer 32 has been deposited and patterned to form the outer electrode of the preferred non-volatile resistance variable device. Example materials include those disclosed in the above Kozicki et al. patents. In the illustrated and described preferred example, silver structure 20 a might be designed and fabricated to constitute the effective quantity of silver for programming the device with no silver being provided in electrode 32. Alternately by way of example only, layer 16 might also constitute elemental silver with no silver being provided in electrode 32. Further, by way of example only, electrode 32 might principally comprise elemental silver, or at least a lower silver portion in contact with the chalcogenide material 27.

The above-described preferred embodiment example was in conjunction with fabrication of a non-volatile resistance variable device. However, the invention also contemplates metal doping a chalcogenide material independent of the device being fabricated, and in the context of the accompanying claims as literally worded regarding methods of metal doping a chalcogenide material. Further, the preferred example is with respect to formation of a projecting metal from an underlying substrate having chalcogenide material received thereover. However, the invention is in no way so limited and also contemplates, by way of example only, diffusing metal from an entirely flat, or other, underlying surface into overlying chalcogenide material.

The invention also contemplates non-volatile resistance variable devices independent of the method of manufacture. In one implementation, such a device includes a projecting metal mass (for example mass 20 a) extending outwardly from a first metal layer laterally central into resistance variable chalcogenide material. In one aspect, the invention contemplates the device being in a highest resistance state for a given ambient temperature and pressure. For example, the FIG. 8 device as depicted is in such a highest state of resistance. Progressively lower states of resistance for a given ambient temperature and pressure will exist as a silver dendrite, in the preferred embodiment, progressively grows from an electrode to the point of contacting the opposing electrode. FIG. 8 depicts but one exemplary embodiment of such a non-volatile resistance variable device having such a laterally central located projecting mass relative to material 27.

The invention also contemplates a non-volatile resistance variable device in a highest resistance state for a given ambient temperature and pressure independent of a conductive projection which is so centrally located. Such comprises a resistance variable chalcogenide material having metal ions diffused therein. Opposing first and second electrodes are received operatively proximate the resistance variable chalcogenide material, with at least one of the electrodes comprising a conductive projection extending into the resistance variable chalcogenide material. Provision of such a structure is in no way shown or suggested in a highest resistance state for a given ambient temperature and pressure in any of the teachings and drawings of the above-described Kozicki et al. patents.

In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. 

1-50. (canceled)
 51. A memory device comprising: a substrate; a first dielectric layer formed over said substrate; a patterned first metal layer formed over said dielectric layer; a second dielectric layer formed laterally adjacent on both sides of said patterned first metal layer; a patterned second metal layer formed over said patterned first metal layer; a chalcogenide layer completely surrounding said patterned second metal layer; an insulating layer formed laterally adjacent on both sides of said chalcogenide layer; and a patterned third metal layer formed over said chalcogenide layer.
 52. The memory device of claim 51, wherein said patterned first metal layer comprises elemental tungsten.
 53. The memory device of claim 52, wherein said elemental tungsten is from about 100 Å to about 1000 Å thick.
 54. The memory device of claim 51, wherein said patterned second metal layer comprises elemental silver.
 55. The memory device of claim 54, wherein said elemental silver is from about 175 Å to about 300 Å thick.
 56. The memory device of claim 51, wherein said patterned second metal layer has an occupied area less than an occupied area of said patterned first metal layer.
 57. The memory device of claim 51, wherein said patterned second metal layer is formed on said patterned first metal layer.
 58. The memory device of claim 51, wherein said chalcogenide layer is from about 525 Å to about 900 Å thick.
 59. The memory device of claim 51, wherein said chalcogenide layer is a metal-doped chalcogenide layer.
 60. The memory device of claim 59, wherein at least a portion of the patterned second metal layer has diffused into said metal-doped chalcogenide layer.
 61. The memory device of claim 51, wherein said patterned third metal layer is formed on said chalcogenide layer.
 62. A programmable resistance memory cell comprising: a semiconductor substrate; a first electrode formed over said semiconductor substrate; a projecting metal mass formed over said first electrode; a metal-doped chalcogenide layer formed over said projecting metal mass that is at least 20% thicker than the projecting metal mass's thickness; and a second electrode formed over said metal-doped chalcogenide layer.
 63. The memory cell of claim 62, wherein said first electrode comprises elemental tungsten that is from about 100 Å to about 1000 Å thick.
 64. The memory cell of claim 62, wherein said projecting metal mass comprises elemental silver that is from about 175 Å to about 300 Å thick.
 65. The memory cell of claim 62, wherein said metal-doped chalcogenide layer is wider than a width of said first electrode and a width of said projecting metal mass in a horizontal direction.
 66. The memory cell of claim 62, wherein said projecting metal mass further comprises a top surface and opposing side surfaces.
 67. The memory cell of claim 66, wherein said metal-doped chalcogenide layer is formed on said top surface.
 68. The memory cell of claim 66, wherein said metal-doped chalcogenide layer is formed laterally adjacent to at least one opposing side surface of said projecting metal mass.
 69. A resistance variable device comprising: a patterned first electrode formed over a semiconductor substrate in a first insulating layer; a metal-doped chalcogenide layer formed over said patterned first electrode in a second insulating layer; a metal layer formed within said metal-doped chalcogenide layer; and a patterned second electrode formed over the metal-doped chalcogenide layer, wherein said patterned first and second electrodes are in electrical communication with each other.
 70. The resistance variable device of claim 69, wherein said patterned first electrode is wider in width than a width of said metal layer formed within said metal-doped chalcogenide layer.
 71. The resistance variable device of claim 69, wherein said metal-doped chalcogenide layer comprises metal ions.
 72. The resistance variable device of claim 71, wherein said metal ions are the same material comprising said metal layer.
 73. The resistance variable device of claim 69, wherein said patterned second electrode is wider in width than a width of said metal layer.
 74. A resistance variable device comprising: a bottom electrode formed over a semiconductor substrate; a metal-doped chalcogenide layer formed at least in part on a portion of said bottom electrode; a metal structure formed within said metal-doped chalcogenide layer; and a top electrode formed on said metal-doped chalcogenide layer.
 75. A resistance variable device comprising: a first and second electrode in electrical communication with each other; a metal-doped chalcogenide layer formed between said first and second electrodes; and a patterned metal layer formed entirely within said metal-doped chalcogenide layer, wherein said patterned metal layer is in physical contact with at least one of said first and second electrodes.
 76. A memory array comprising a plurality of memory cells, at least some memory cells of said array, each comprising: a first electrode; a metal-doped chalcogenide layer formed over said first electrode; a metal structure formed within said metal-doped chalcogenide layer; and a second electrode formed over said metal-doped chalcogenide layer.
 77. The memory array of claim 76, wherein said first electrode comprises elemental tungsten.
 78. The memory array of claim 77, wherein said elemental tungsten is from about 100 Å to about 1000 Å thick.
 79. The memory array of claim 76, wherein said second electrode comprises elemental tungsten.
 80. The memory array of claim 79, wherein said elemental tungsten is from about 100 Å to about 1000 Å thick.
 81. The memory array of claim 76, wherein said metal structure comprises elemental silver.
 82. The memory array of claim 81, wherein said elemental silver is from about 175 Å to about 300 Å thick.
 83. The memory array of claim 76, wherein said metal structure is smaller in width than the metal-doped chalcogenide layer's width in a horizontal direction.
 84. The memory array of claim 76, wherein said metal structure is smaller in width than the first electrode's width in a horizontal direction.
 85. The memory array of claim 76, wherein said metal-doped chalcogenide layer is from about 525 Å to about 900 Å thick.
 86. The memory array of claim 76, wherein said metal-doped chalcogenide layer comprises metal ions from said metal structure.
 87. The memory array of claim 76, wherein at least a portion of the metal structure has diffused into said metal-doped chalcogenide layer.
 88. The memory array of claim 76, wherein said first electrode is in contact with said metal-doped chalcogenide layer.
 89. The memory array of claim 76, wherein said first electrode is in contact with said metal structure.
 90. The memory array of claim 76, wherein said second electrode is in contact with said metal-doped chalcogenide layer.
 91. The memory array of claim 76, wherein said second electrode is in contact with said metal structure.
 92. A memory array comprising a plurality of programmable resistance cells, at least some of said programmable resistance cells, each comprising: a first and second electrode formed over a semiconductor substrate, wherein said first and second electrodes are in electrical communication with each other; a metal-doped chalcogenide layer formed between said first and second electrodes; and a projecting metal mass formed entirely within said metal-doped chalcogenide layer.
 93. A memory cell comprising: a first and second electrode formed over a semiconductor substrate, wherein said first and second electrodes are in electrical communication with each other; a metal-doped chalcogenide layer formed between said first and second electrodes; and a metal structure formed entirely within said metal-doped chalcogenide layer.
 94. The memory cell of claim 93, wherein said first electrode comprises elemental tungsten.
 95. The memory cell of claim 94, wherein said elemental tungsten is from about 100 Å to about 1000 Å thick.
 96. The memory cell of claim 93, wherein said second electrode comprises elemental tungsten.
 97. The memory cell of claim 96, wherein said elemental tungsten is from about 100 Å to about 1000 Å thick.
 98. The memory cell of claim 93, wherein said metal structure comprises elemental silver.
 99. The memory cell of claim 98, wherein said elemental silver is from about 175 Å to about 300 Å thick.
 100. The memory cell of claim 93, wherein said metal structure is smaller in width than the metal-doped chalcogenide layer's width in a horizontal direction.
 101. The memory cell of claim 93, wherein said metal structure is smaller in width than the first electrode or second electrode's width in a horizontal direction.
 102. The memory cell of claim 93, wherein said metal-doped chalcogenide layer is from about 525 Å to about 900 Å thick.
 103. The memory cell of claim 93, wherein said metal-doped chalcogenide layer comprises metal ions from said metal structure.
 104. The memory cell of claim 103, wherein at least a portion of the metal structure has diffused into said metal-doped chalcogenide layer.
 105. The memory array of claim 76, wherein said first electrode is in contact with said metal-doped chalcogenide layer.
 106. The memory cell of claim 93, wherein said first electrode is in contact with said metal structure.
 107. The memory cell of claim 93, wherein said second electrode is in contact with said metal-doped chalcogenide layer.
 108. The memory cell of claim 93, wherein said second electrode is in contact with said metal structure. 